Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

Shin Hung Chen*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
Pages245-248
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India
Duration: 11 Jul 200713 Jul 2007

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
CountryIndia
CityBangalore
Period11/07/0713/07/07

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