Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)

Vita Pi Ho Hu*, Hung Han Lin, Yen Kai Lin, Chenming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

We investigate the GaAs0.51Sb0.49/In0.53Ga0.47As negative-capacitance vertical-tunnel FET (NCVT-FET) to maximize its vertical tunneling over the corner tunneling. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. By TCAD optimization of the device, small {I}_{{\mathrm {OFF}}} (10 pA/ \mu \text{m} ) and large {I}_{\text{ON}} ( 405~\mu \text{A}/\mu \text{m} ) at {V}_{\text {DD}} = {0.5} V with 14 mV/dec sub- {V}_{\text {t}} swing over 4 dec of current were obtained. Even at {V}_{\text {DD}} ={0.1} V, the optimized NCVT-FET has 10 pA/ \mu \text{m}~{I}_{\text{OFF}} , 5.86~\mu \text{A}/\mu \text{m}~{I}_{\text{ON}} ( 144\times higher than the nominal TFET), and {I}_{\text{ON}}/{I}_{\text{OFF}} ratio of {6} \times {10}^{{5}}.

Original languageEnglish
Article number9079209
Pages (from-to)2593-2599
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume67
Issue number6
DOIs
StatePublished - Jun 2020

Keywords

  • Ferroelectric (FE)
  • Heterojunction
  • Negative capacitance (NC)
  • Tunnel FET (TFET)

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