Optimization of epitaxial layers for power bipolar-mos transistor

Di Son Kuo, Chen-Ming Hu

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

This is a theoretical study of the effect of epitaxial layer design on the performance of the power bipolar-MOS transistor, also known as IGT and COMFET. A procedure for optimizing the layer thicknesses, doping concentrations, and lifetime is proposed and examples are provided for 500-V devices. The use of a thin (<5 μm) and rather heavily doped (~1018 cm-3) buffer layer can have pronounced beneficial effects on device turn-off speed and a small benefit on the forward voltage. Turn-off time can be much shorter than the carrier lifetime due to a low emitter efficiency. For the same forward-voltage performance, using an optimally designed buffer layer gives much faster device switching speed than using lifetime control. By combining the use of optimally designed epitaxial layer and carrier lifetime reduction, it is possible to achieve 100-ns switching speed while maintaining low forward-voltage drop.

Original languageEnglish
Pages (from-to)510-512
Number of pages3
JournalIEEE Electron Device Letters
Volume7
Issue number9
DOIs
StatePublished - 1 Jan 1986

Fingerprint Dive into the research topics of 'Optimization of epitaxial layers for power bipolar-mos transistor'. Together they form a unique fingerprint.

Cite this