Optimal structure of interconnection lines for GHz gaiga-scale nano-CMOS system-on-chip design

Chung-Yu Wu*, Jen Chieh Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

As CMOS technology is scaled down to below 90 nm, interconnection lines on a complicated chip plays a very key role in speed/frequency and performance. The conventional coplanar interconnection structure has good high-frequency performance, but the chip area is large. This will significantly increase chip area of a complicated System-On-Chip (SOC) which require many interconnection lines. In this research, the optimal structure of interconnection lines for nano-CMOS technology with multi-layer metals is proposed and analyzed. It is found from simulation results that multi-layer non-coplanar interconnection lines with signal line at the top layer metal and ground line at a lower layer metal without planar space between lines have the optimal performance of transmission loss, frequency response, and chip area. Experimental chip will be designed to verify the simulation results. The proposed new interconnection structure can be applied to nano-CMOS SOC design.

Original languageEnglish
Title of host publication11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004
Pages191-194
Number of pages4
DOIs
StatePublished - 1 Dec 2004
Event11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004 - Tel Aviv, Israel
Duration: 13 Dec 200415 Dec 2004

Publication series

Name11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004

Conference

Conference11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004
CountryIsrael
CityTel Aviv
Period13/12/0415/12/04

Fingerprint Dive into the research topics of 'Optimal structure of interconnection lines for GHz gaiga-scale nano-CMOS system-on-chip design'. Together they form a unique fingerprint.

Cite this