Optimal Floating Gate Potential for Extending Data Retention of Post-Baking Method in Sub-20 nm Triple Level per Cell NAND Flash Memory

Yu Cheng Hsu, Wei Lin, Chun-Yen Chang

Research output: Contribution to journalArticlepeer-review

Abstract

A post-baking method with an optimized data pattern is developed to eliminate the program/erase (PE) cycle-induced damage of sub-20 nm NAND Flash memory and to improve its reliability. The electric field of the tunneling oxide (E-ox)-dependent oxide recovery is discussed in detail. The experimental results reveal that additional traps in the tunneling oxide are induced by the E-ox during the baking process via an electron-phonon interaction and the effectiveness of oxide recovery is reduced by the generation of these additional traps. Hence, the additional traps degrade the read margin and retention ability. Therefore, an optimized data pattern is produced to minimize E-ox and reduce the number of additional traps formed during the post-baking process. When the optimized data pattern is utilized in post-baking, the endurance of the sub-20 nm three-level-per-cell (TLC) NAND Flash memory is quadruple improved under one year retention condition.
Original languageEnglish
Pages (from-to)7295-7300
Number of pages6
JournalJournal of Nanoscience and Nanotechnology
Volume16
Issue number7
DOIs
StatePublished - Jun 2016

Keywords

  • NAND Flash Memory; Program/Erase (PE) Cycling; Post-Baking Method
  • TRAP GENERATION; INTERFACE; ELECTRON; OXIDE

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