This paper investigates diagnosis strategies for repairable VLSI and WSI structures based on integrated diagnosis and repair. Knowledge of the repair strategy, the probability of each unit being good, and the expected test time of each unit is used by the diagnosis algorithm to select units for testing. The general problem is described followed by an examination of a specific case. For k-out-of-n structures, we give a complete proof for the optimal diagnosis procedure proposed by Ben-Dov. A compact representation of the optimal diagnosis procedure is described, which requires O(n2) space and can be generated in O(n2) time. Simulation results are provided to show the improvement in diagnosis time over on-line repair and off-line repair.
- wafer probe testing