Optimal design of triple-gate devices for high-performance and low-power applications

Meng-Hsueh Chiang, Jeng-Nan Lin, Keunwoo Kim, Ching-Te Chuang

Research output: Contribution to journalArticle

6 Scopus citations

Abstract

Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V-T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.
Original languageEnglish
Pages (from-to)2423-2428
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume55
Issue number9
DOIs
StatePublished - Sep 2008

Keywords

  • corner effects; polysilicon gate; triple-gate (TG); MOSFETs
  • CMOS

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