Optimal design of triple-gate devices for high-performance and low-power applications

Meng-Hsueh Chiang; Jeng-Nan Lin; Keunwoo Kim; Ching-Te Chuang

doi:10.1109/TED.2008.927664

Optimal design of triple-gate devices for high-performance and low-power applications

Meng-Hsueh Chiang, Jeng-Nan Lin, Keunwoo Kim, Ching-Te Chuang

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V-T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.

Original language	English
Pages (from-to)	2423-2428
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	55
Issue number	9
DOIs	https://doi.org/10.1109/TED.2008.927664
State	Published - Sep 2008

Keywords

corner effects; polysilicon gate; triple-gate (TG); MOSFETs
CMOS

Access to Document

10.1109/TED.2008.927664

Fingerprint Dive into the research topics of 'Optimal design of triple-gate devices for high-performance and low-power applications'. Together they form a unique fingerprint.

Cite this

@article{f5c4eb006af241c48f9097667613e443,

title = "Optimal design of triple-gate devices for high-performance and low-power applications",

abstract = "Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V-T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.",

keywords = "corner effects; polysilicon gate; triple-gate (TG); MOSFETs, CMOS",

author = "Meng-Hsueh Chiang and Jeng-Nan Lin and Keunwoo Kim and Ching-Te Chuang",

year = "2008",

month = sep,

doi = "10.1109/TED.2008.927664",

language = "English",

volume = "55",

pages = "2423--2428",

journal = "Ieee Transactions On Electron Devices",

issn = "0018-9383",

publisher = "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC",

number = "9",

}

TY - JOUR

T1 - Optimal design of triple-gate devices for high-performance and low-power applications

AU - Chiang, Meng-Hsueh

AU - Lin, Jeng-Nan

AU - Kim, Keunwoo

AU - Chuang, Ching-Te

PY - 2008/9

Y1 - 2008/9

N2 - Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V-T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.

AB - Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical (n(+)/p(+)) polysilicon gates. CMOS-compatible V-T's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.

KW - corner effects; polysilicon gate; triple-gate (TG); MOSFETs

KW - CMOS

U2 - 10.1109/TED.2008.927664

DO - 10.1109/TED.2008.927664

M3 - Article

VL - 55

SP - 2423

EP - 2428

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

SN - 0018-9383

IS - 9

ER -