Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulation-based multi-objective evolutionary algorithm

Yi Hsuan Hung, Sheng Chin Hung, Chien Hsueh Chiang, Yiming Li*

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

A short rise time, short fall time, and small ripple are required to reduce the misoperation of pixel data voltage and to improve the stable signal processing of a driver circuit. In this study, a novel amorphous silicon gate (ASG) driver circuit consisting of 15 hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) and two capacitors was optimized using a thin-film transistor (TFT)-circuit-simulation-based multi-objective evolutionary algorithm on the unified optimization framework. The ASG circuit was optimized for the following given specifications: rise time <0.7µs; fall time <0.6µs; ripple peak <6.5V; clock Ctotal <40pf; and total TFT widths <6000µm. The main findings of this study show that the rise time had an 18% reduction and that the fall time, total widths, and clock Ctotal had 7, 17.5, and 9% reductions, respectively.

Original languageEnglish
Pages (from-to)51-58
Number of pages8
JournalJournal of Information Display
Volume17
Issue number2
DOIs
StatePublished - 2 Apr 2016

Keywords

  • amorphous silicon gate (ASG) driver circuits
  • Amorphous silicon thin-film transistor (TFT)
  • display panel
  • drive circuit design
  • dynamic characteristics
  • multi-objective evolutionary algorithm (MOEA)
  • unified optimization framework (UOF)

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