Operation of CMOS Devices with a Floating Well

Hans P. Zappe, Rajesh K. Gupta, Chen-Ming Hu, Sami Sakai

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area consumption and wiring complexity involved in contacting the well diffusion. Theoretical expectations for device behavior are presented and corroborated with experimental data; consideration extends to PMOSFET device characteristics, subthreshold behavior, as well as junction leakage and breakdown voltage. Examination of n-channel devices, in p-wells, indicates that these are more susceptible to floating well effects, as expected. The primary changes in device behavior include generation of substrate current, slight increase in leakage currents, and some degradation in latchup holding voltage. Results indicate that an electrically floating well does not seem to have significant adverse effects on transistor operation.

Original languageEnglish
Pages (from-to)335-343
Number of pages9
JournalIEEE Transactions on Electron Devices
Issue number2
StatePublished - 1 Jan 1987

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