One-Transistor Ferroelectric Versatile Memory: Strained-Gate Engineering for Realizing Energy-Efficient Switching and Fast Negative-Capacitance Operation

Yu Chien Chiu, Chun-Hu Cheng, Chun-Yen Chang, Ying-Tsan Tang, Min Cheng Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by similar to 47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over similar to 4 decade of I-D to provide a 1 similar to 10 fA/mu m I-off and >10(8) I-on/I-off ratio, which allows for a fast 20-ns P/E switching during 10(12) cycling endurance.
Original languageEnglish
Title of host publication36th IEEE Symposium on VLSI Technology
DOIs
StatePublished - 2016

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