On VLSI design of rank-order filtering using DCRAM architecture

Meng Chun Lin*, Lan-Rong Dung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18 μ m 1P6M technology. As shown in the result of physical implementation, the core size is 356.1 × 427.7 μ m2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8 V supply.

Original languageEnglish
Pages (from-to)193-209
Number of pages17
JournalIntegration, the VLSI Journal
Issue number2
StatePublished - 1 Feb 2008


  • CMOS memory integrated circuits
  • Coprocessors
  • Image processing
  • Median filters
  • Nonlinear filters

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