This paper describes a leading-edge 0.13μm low-leakage CMOS logic foundry technology. To achieve competitive off-state leakage current (Ioff) and gate delay (Td) performance at operation voltages (Vdd) 1.5V and 1.2V, devices with 0.11 μm nominal gate length (Lg_nom) and various gate oxide thickness (Tox) were fabricated and studied. The results show that low power and memory applications are limited to oxides thicker than 21-22 Å in order to keep acceptable off-state power consumption at Vdd=1.2V. Specifically two different device designs are introduced here. One design named LP (Tox=26Å) is targeted for Vdd=1.5 with worst case Ioff < 10pA/μm and nominal gate delay 24ps/gate. Another design, named LP1 (Tox=22Å) is targeted for Vdd=1.2V with worst case Ioff < 20pA/μm and nominal gate delay 27ps/gate. This work demonstrates n/pMOSFETs with 520/210 and 390/160 μA/μm nominal drive currents ♀dd_nom for LP and LP1, respectively. Process capability for low power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm2 cell size. Measured standby currents are 3.6 and 6.9 pA/cell ♀dd_nom for LP and LP1 respectively at room temperature.
|Number of pages||4|
|State||Published - 2001|
|Event||9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems - Singapore, Singapore|
Duration: 3 Sep 2001 → 5 Sep 2001
|Conference||9th International Symposium on Integrated Circuits, Devices and Systems, ISIC 2001: Proceedings - Low Power and Low Voltage Integrated Systems|
|Period||3/09/01 → 5/09/01|