On the reduction of reorder buffer size for discrete Fourier transform processor design

Wen Zen Shen*, Yi Hsin Tao, Lan-Rong Dung

*Corresponding author for this work

Research output: Contribution to journalConference article

3 Scopus citations

Abstract

Double RAM buffer technique is widely used in row-column method to decompose the multidimensional transformation. In this paper, we propose a new approach, named single RAM technique. Base on the accurate arrangement of the location and timing of the input and output data, only a single RAM is used as the reorder buffer. Therefore, approximately half of the memory size is reduced. In addition, a long length DFT processor which can handle 1008-point real-valued DFT with nonstop input sequence is presented to demonstrate the benefits of the single RAM buffer technique. Goertzel Algorithm and CORDIC technique are adopted to realize a two level pipeline linear array for attaining higher speed. Besides, based on the symmetric property of real value DFT, we can compute N-point real-valued DFT with a length-N/2 complex-valued DFT.

Original languageEnglish
Pages (from-to)171-174
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
DOIs
StatePublished - 1 Dec 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: 30 May 19942 Jun 1994

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