On the design of power-rail ESD clamp circuits with gate leakage consideration in nanoscale CMOS technology

Ming-Dou Ker, Chih Ting Yeh

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

CMOS technology has been widely used to produce many integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously increases the difficulty of electrostatic discharge (ESD) protection design. The power-rail ESD clamp circuit has been the key circuit to perform the whole-chip ESD protection scheme. Some ESD detection circuits were developed to trigger on ESD devices across the power rails to quickly discharge ESD current away from the internal circuits. Therefore, on-chip ESD protection circuits must be designed with the consideration of standby leakage to minimize the power consumption and the possibility of malfunction to normal circuit operation. The design of power-rail ESD clamp circuits with low standby leakage current and high efficiency of layout area in nanoscale CMOS technology is reviewed in this paper. The comparisons among those power-rail ESD clamp circuits are also discussed.

Original languageEnglish
Article number6587810
Pages (from-to)536-544
Number of pages9
JournalIEEE Transactions on Device and Materials Reliability
Volume14
Issue number1
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Electrostatic discharge (ESD)
  • Power-rail ESD clamp circuit
  • gate leakage
  • layout area

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