On the body-source built-in potential lowering of SOI MOSFETs

Pin Su; Samuel K.H. Fung; Peter W. Wyatt; Hui Wan; Ali M. Niknejad; Mansun Chan; Chen-Ming Hu

doi:10.1109/LED.2002.807696

On the body-source built-in potential lowering of SOI MOSFETs

Pin Su^*, Samuel K.H. Fung, Peter W. Wyatt, Hui Wan, Ali M. Niknejad, Mansun Chan, Chen-Ming Hu

^*Corresponding author for this work

Research output: Contribution to journal › Article

15 Scopus citations

Abstract

This letter provides a viewpoint for the characterization of state-of-the-art thin film sllicon-on-insulator (SOI) MOSFETs. Based on body - source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.

Original language	English
Pages (from-to)	90-92
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	24
Issue number	2
DOIs	https://doi.org/10.1109/LED.2002.807696
State	Published - 1 Feb 2003

Keywords

Body-source built-in potential lowering
Floating-body effect
Impact ionization
Silicon-film-thickness scaling
SOI CMOS

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10.1109/LED.2002.807696

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Su, P., Fung, S. K. H., Wyatt, P. W., Wan, H., Niknejad, A. M., Chan, M., & Hu, C-M. (2003). On the body-source built-in potential lowering of SOI MOSFETs. IEEE Electron Device Letters, 24(2), 90-92. https://doi.org/10.1109/LED.2002.807696

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