The debugging is the design gap bottleneck of today’s complex HDL (Hardware Description Language) design. Base on the design and simulation dumping, this paper proposes an automatic bug diagnosis method. By analyzing the difference between the output signals wave forms of HDL design and the design 10 timing specification, each HDL statement is given a weight indicating the degree of probability of a bug. The experiments show that our approach can identify a bug with 89% accuracy.
|Number of pages||13|
|Journal||Journal of Discrete Mathematical Sciences and Cryptography|
|State||Published - 1 Jan 2005|
- Asic design
- Inference synthesis