On the automatic HDL bug identification

Ming Chih Lai*, Yih-Lang Li, Shyan-Ming Yuan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


The debugging is the design gap bottleneck of today’s complex HDL (Hardware Description Language) design. Base on the design and simulation dumping, this paper proposes an automatic bug diagnosis method. By analyzing the difference between the output signals wave forms of HDL design and the design 10 timing specification, each HDL statement is given a weight indicating the degree of probability of a bug. The experiments show that our approach can identify a bug with 89% accuracy.

Original languageEnglish
Pages (from-to)413-425
Number of pages13
JournalJournal of Discrete Mathematical Sciences and Cryptography
Issue number3
StatePublished - 1 Jan 2005


  • Asic design
  • Debug
  • HDL
  • Inference synthesis
  • Reasoning
  • Simulation
  • Verification

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