On reducing test power and test volume by selective pattern compression schemes

Chia Yi Lin*, Hsiu Chuan Lin, Hung-Ming Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

10 Scopus citations

Abstract

In modern chip designs, test strategies are becoming one of the most important issues due to the increase of the test cost, among them we focus on the large test power dissipation and large test data volume. In this paper, we develop a methodology to suppress the test power to avoid chip failures caused by large test power, and our methodology is also effective in reducing the test data volume and shift-in power. The proposed schemes and techniques are based on the selective test pattern compression, they can reduce considerable shift-in power by skipping the switching signal passing through long scan chains. The experimental results with ISCAS89 circuits demonstrate that our methodology can achieve significant improvement in the reduction of shift-in power and test data volume. Our approach also supports multiple scan chains.

Original languageEnglish
Article number5229137
Pages (from-to)1220-1224
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume18
Issue number8
DOIs
StatePublished - 1 Aug 2010

Keywords

  • Compression
  • DFT
  • low power
  • scan chain
  • test data volume

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