On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process

Ming-Dou Ker*, Jie Yao Chuang, Chih Kang Deng, Chung Hong Kuo, Chun Huai Li, Ming Sheng Lai, Chih Wei Wang, Chun Ting Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The electrostatic discharge (ESD) robustness of diode-connected n-type thin-film transistors (N-TFTs) and diode-connected p-type thin-film transistors (P-TFTs) with different layout structures in a given low-temperature polycrystalline silicon (LTPS) process is investigated. By using the wafer-level transmission line pulsing (TLP) system, the high-current transient characteristics and the secondary breakdown current (It2) levels of the diode-connected TFTs under different device parameters and layout structures are directly measured on the glass substrate. Finally, one set of design rules for on-panel ESD protection design is suggested.

Original languageEnglish
Title of host publicationAD'07 - Proceedings of Asia Display 2007
Pages551-556
Number of pages6
StatePublished - 1 Dec 2007
EventAsia Display 2007, AD'07 - Shanghai, China
Duration: 12 Mar 200716 Mar 2007

Publication series

NameAD'07 - Proceedings of Asia Display 2007
Volume1

Conference

ConferenceAsia Display 2007, AD'07
CountryChina
CityShanghai
Period12/03/0716/03/07

Keywords

  • Electrostatic discharge (ESD)Transmission line pulsing (TLP) system
  • Low-temperature polycrystalline silicon (LTPS)
  • Thin-film transistors (TFTs)

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