On multiple-voltage high-level synthesis using algorithmic transformations

Lan-Rong Dung*, Hsueh Chih Yang

*Corresponding author for this work

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

This paper presents a multiple-voltage high-level synthesis approach for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by maximization of task mobilities in that the increase of mobilities may raise the possibility of assigning tasks to low-voltage components. The mobility means the ability to schedule the starting time of a task. It is defined as the distance between its as-late-as-possible (ALAP) schedule time and its as-soon-as-possible (ASAP) schedule time. To earn task mobilities, we use loop shrinking, retiming and unfolding techniques. The loop shrinking can first reduce the iteration period bound (IPB) and, then, the others are employed for shortening the iteration period (IP) as much as possible. The minimization of IP results in high task mobilities. Finally, we can assign tasks with high mobilities to low-voltage components and, thus, minimize energy under resource and latency constraints. With considering the overhead of level conversion, our approach can achieve significant power reduction. In the case of the third-order IIR filter, the proposed approach can save up to 40.2% of power consumption.

Original languageEnglish
Pages (from-to)3100-3108
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
VolumeE87-A
Issue number12
StatePublished - 1 Dec 2004

Keywords

  • High-level synthesis
  • Loop shrinking
  • Low-power circuit
  • Multiple voltage scheduling
  • Retiming
  • Unfolding

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