On multiple-voltage high-level synthesis using algorithmic transformations

Hsueh Chih Yang*, Lan-Rong Dung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

This paper presents a multiple-voltage high-level synthesis methodology for low power DSP applications using algorithmic transformation techniques. Our approach is motivated by maximization of task mobilities in that the increase of mobilities may raise the possibility of assigning tasks to low-voltage components. The mobility means the ability to schedule the starting time of a task. It is defined as the distance between its as-late-as-possible (ALAP) schedule time and its as-soon-as-possible (ASAP) schedule time. To earn task-mobilities, we use loop shrinking, retiming and unfolding techniques. The loop shrinking can first reduce the iteration period bound (IPB) and, then, the others are employed for shortening the minimum achieved sample period (MASP) as much as possible. The minimization of MASP results in high task mobilities. Thereafter, we can assign tasks with high mobilities to low-voltage components and minimize energy dissipation under resource and latency constraints. With considering the overhead of level conversion, our approach can achieve significant power reduction. For instance, as the experimental results, we can save the power consumption up to 54.77% for the case of the third-order IIR filter.

Original languageEnglish
Title of host publicationProceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages872-876
Number of pages5
DOIs
StatePublished - 18 Jan 2005
Event2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China
Duration: 18 Jan 200521 Jan 2005

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2

Conference

Conference2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
CountryChina
CityShanghai
Period18/01/0521/01/05

Keywords

  • High-level synthesis
  • Loop shrinking
  • Low power circuit
  • Multiple voltage scheduling
  • Retiming
  • Unfolding

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    Yang, H. C., & Dung, L-R. (2005). On multiple-voltage high-level synthesis using algorithmic transformations. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 872-876). [1466479] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2). https://doi.org/10.1109/ASPDAC.2005.1466479