On minimizing various sources of noise and meeting symmetry constraint in mixed-signal SoC floorplan design

Chung Hsin Lin*, Hung-Ming Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC f oorplan with the twophase approach. In the f rst phase, we place the symmetry groups and non-symmetry blocks by sequence pair representation with improved implementation. In the second phase, we obtain a f oorplan with minimized digital blocks noise interference to analog blocks by the effective decap f lls with substrate noise model. We have compared our experimental results with the recent works in symmetry constraints and mixed-signal SOC f oorplan with minimized substrate noise. The results demonstrate the effectiveness of our approach.

Original languageEnglish
Title of host publication2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009
Pages96-102
Number of pages7
DOIs
StatePublished - 19 Nov 2009
Event2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009 - Kuala Lumpur, Malaysia
Duration: 15 Jul 200916 Jul 2009

Publication series

Name2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009

Conference

Conference2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009
CountryMalaysia
CityKuala Lumpur
Period15/07/0916/07/09

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    Lin, C. H., & Chen, H-M. (2009). On minimizing various sources of noise and meeting symmetry constraint in mixed-signal SoC floorplan design. In 2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009 (pp. 96-102). [5206291] (2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009). https://doi.org/10.1109/ASQED.2009.5206291