On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design

Chao Hung Lu; Hung-Ming Chen; Chien-Nan Liu

doi:10.1109/ASPDAC.2007.358086

On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design

Chao Hung Lu^*, Hung-Ming Chen, Chien-Nan Liu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during early design stage in area-array designs. The experimental results are encouraging. Compared with other approaches in [15] and [12], we have inserted enough decap to meet supply noise constraint while others employ more area.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Pages	792-797
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2007.358086
State	Published - 1 Dec 2007
Event	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan Duration: 23 Jan 2007 → 27 Jan 2007

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Country	Japan
City	Yokohama
Period	23/01/07 → 27/01/07

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10.1109/ASPDAC.2007.358086

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Lu, C. H., Chen, H-M., & Liu, C-N. (2007). On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design. In Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 (pp. 792-797). [4196132] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2007.358086

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title = "On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design",

abstract = "With technology further scaling into deep submicron era, power supply noise become an important problem. Power supply noise problem is getting worse due to serious IR-drop and simultaneous switching noise, and decoupling capacitance (decap) insertion is commonly applied to alleviate the noise. There exist some approaches to addressing this issue, but they suffer either from over-design problem or late decap insertion during design stage. In this paper, we propose a methodology to insert decap in a more efficient and effective way during early design stage in area-array designs. The experimental results are encouraging. Compared with other approaches in [15] and [12], we have inserted enough decap to meet supply noise constraint while others employ more area.",

author = "Lu, {Chao Hung} and Hung-Ming Chen and Chien-Nan Liu",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/ASPDAC.2007.358086",

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Lu, CH, Chen, H-M & Liu, C-N 2007, On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design. in Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007., 4196132, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 792-797, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 23/01/07. https://doi.org/10.1109/ASPDAC.2007.358086

On increasing signal integrity with minimal decap insertion in area-array SoC floorplan design. / Lu, Chao Hung; Chen, Hung-Ming ; Liu, Chien-Nan.

Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007. 2007. p. 792-797 4196132 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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