On-demand memory sub-system for multi-core SoCs

Po-Tsang Huang*, Yung Chang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sub-system is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.

Original languageEnglish
Title of host publicationProceedings - IEEE International SOC Conference, SOCC 2011
Pages122-127
Number of pages6
DOIs
StatePublished - 28 Dec 2011
Event24th IEEE International System on Chip Conference, SOCC 2011 - Taipei, Taiwan
Duration: 26 Sep 201128 Sep 2011

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference24th IEEE International System on Chip Conference, SOCC 2011
CountryTaiwan
CityTaipei
Period26/09/1128/09/11

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