On circuit clustering for area/delay tradeoff under capacity and pin constraints

Juinn-Dar Huang*, Jing Yang Jou, Wen Zen Shen, Hsien Ho Chuang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depth-first-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performance. We then show that this algorithm can be easily extended to solve the clustering problem subject to both capacity and pin constraints. Experimental results show that our algorithm can provide a complete set of clustering solutions from the area-optimized one to the delay-optimized one for a given circuit. Furthermore, comparing to the existing delay-optimized algorithms, ours achieves almost the same performance but with much less area overhead. Therefore, this algorithm is very useful on solving the timing-driven circuit clustering problem.

Original languageEnglish
Pages (from-to)634-642
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume6
Issue number4
DOIs
StatePublished - 1 Dec 1998

Keywords

  • Clustering
  • Critical path
  • Delay
  • Partitioning
  • Performance
  • Performance tradeoffs

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