On-chip transient detection circuit for system-level ESD protection in CMOS ICs

Ming-Dou Ker*, Cheng Cheng Yen, Pi Chia Shih

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages361-364
Number of pages4
DOIs
StatePublished - 1 Dec 2006
EventIEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States
Duration: 10 Sep 200613 Sep 2006

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

ConferenceIEEE 2006 Custom Integrated Circuits Conference, CICC 2006
CountryUnited States
CitySan Jose, CA
Period10/09/0613/09/06

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