On-chip memory module designs for video-signal processing

Tian-Sheuan Chang*, C. W. Jen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Two embedded memory designs are proposed for video-signal processing. Concurrent line access performs multiple-port memory accesses at the hardware cost and access time of a single port. It uses 62.24% of the area required by a conventional dual-port memory and is only 7.6% larger than a single-port 2K x 8 memory. The block-access mode combines address decoders and generators, yielding block-access mode times 26% faster than conventional schemes for a 256 words x 32 bits memory size. Despite some preferred-access-order restrictions, the designs incur no loss of generality because video algorithms possess high data parallelism and low dependence.

Original languageEnglish
Pages (from-to)138-144
Number of pages7
JournalIEE Proceedings: Circuits, Devices and Systems
Volume144
Issue number3
DOIs
StatePublished - 1 Jan 1997

Keywords

  • On-chip memory designs
  • Video-signal processing

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