On-chip, interconnect capacitance characterization method with sub-femto-farad resolution

James C. Chen*, Dennis Sylvester, Chen-Ming Hu, Hitoshi Aoki, Sam Nakagawa, Soo Young Oh

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

18 Scopus citations

Abstract

In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3-D simulations.

Original languageEnglish
Pages77-80
Number of pages4
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 IEEE International Conference on Microelectronic Test Structures, ICMTS - Monterey, CA, USA
Duration: 17 Mar 199720 Mar 1997

Conference

ConferenceProceedings of the 1997 IEEE International Conference on Microelectronic Test Structures, ICMTS
CityMonterey, CA, USA
Period17/03/9720/03/97

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