In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3-D simulations.
|Number of pages||4|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 IEEE International Conference on Microelectronic Test Structures, ICMTS - Monterey, CA, USA|
Duration: 17 Mar 1997 → 20 Mar 1997
|Conference||Proceedings of the 1997 IEEE International Conference on Microelectronic Test Structures, ICMTS|
|City||Monterey, CA, USA|
|Period||17/03/97 → 20/03/97|