On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Ming-Dou Ker*, Chung-Yu Wu, Tao Cheng, Michael J.N. Wu, Ta Lee Yu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

4 Scopus citations

Abstract

Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

Original languageEnglish
Pages (from-to)135-138
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - 1 Dec 1995
EventProceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA
Duration: 18 Sep 199522 Sep 1995

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