On-chip ESD protection designs in RF integrated circuits for radio and wireless applications

Ming-Dou Ker, Chun Yu Lin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.

Original languageEnglish
Title of host publication2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
DOIs
StatePublished - 23 Dec 2013
Event2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 - Hong Kong, Hong Kong
Duration: 3 Jun 20135 Jun 2013

Publication series

Name2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013

Conference

Conference2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013
CountryHong Kong
CityHong Kong
Period3/06/135/06/13

Keywords

  • Electrostatic discharge (ESD)
  • low capacitance
  • radio-frequency (RF)

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    Ker, M-D., & Lin, C. Y. (2013). On-chip ESD protection designs in RF integrated circuits for radio and wireless applications. In 2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013 [6628166] (2013 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2013). https://doi.org/10.1109/EDSSC.2013.6628166