On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

Tai Ho Wang*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

7 Scopus citations

Abstract

A novel on-chip ESD protection design by using polysilicon diodes for smart card application is reported in this paper. By adding an efficient VDD-to-VSS clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original approximately 300 V to become ≥3 kV. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing, the polysilicon diodes for both smart card application and on-chip ESD protection design.

Original languageEnglish
Pages (from-to)266-275
Number of pages10
JournalElectrical Overstress/Electrostatic Discharge Symposium Proceedings
StatePublished - 1 Dec 2000
EventElectrical Overstress/Electrostatic Discharge Symposium Proceedings - Anaheim, CA, USA
Duration: 26 Sep 200028 Sep 2000

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