On-chip ESD protection design by using polysilicon diodes in CMOS process

Ming-Dou Ker*, Tung Yang Chen, Tai Ho Wang, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

22 Scopus citations

Abstract

A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is first proposed in this paper. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-pulse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ∼300 V to become ≥3 kV. This design has been practically applied in a mass-production smart-card IC.

Original languageAmerican English
Pages (from-to)676-686
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume36
Issue number4
DOIs
StatePublished - 1 Apr 2001

Keywords

  • ESD protection circuit
  • Electrostatic discharge (ESD)
  • Polysilicon diode
  • Smart card
  • Transmission-line-pulse (TLP) generator

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