On-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs

Ming-Dou Ker*, Chung-Yu Wu, Hsin Chin Jiang, Chung Yuan Lee, Joe Ko, Peter Hsue

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

A new on-chip ESD protection circuit with complementary SCR structures is proposed. This circuit can provide ESD protection above ±6500V and ±400V in human-body-mode and machine-mode ESD stresses, respectively, with the total layout area of 108μm × 242μm including the latchup guard-ring of 10 - μm width and a 90μm × 90μm metal pad for wire bonding.

Original languageEnglish
Pages1145-1148
Number of pages4
StatePublished - 1 Dec 1994
EventProceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2) - Lafayette, LA, USA
Duration: 3 Aug 19945 Aug 1994

Conference

ConferenceProceedings of the 37th Midwest Symposium on Circuits and Systems. Part 2 (of 2)
CityLafayette, LA, USA
Period3/08/945/08/94

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