On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

Ming-Dou Ker*, Kuo Chun Hsu

*Corresponding author for this work

Research output: Contribution to journalConference article

5 Scopus citations

Abstract

A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-μm CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40μm×20μm can sustain the HBM ESD stress of higher than 7kV.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
DOIs
StatePublished - 1 Jan 2002
Event2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States
Duration: 26 May 200229 May 2002

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