In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01fF or 10 aF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. The measurement itself is also simple; only a DC current meter is required. We have applied this technique to extract various interconnect geometry capacitances, including the capacitance of a single Metal 2 over Metal 1 crossing, for an industrial double metal process.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 IEEE International Electron Devices Meeting - San Francisco, CA, USA|
Duration: 8 Dec 1996 → 11 Dec 1996