On-board fault-tolerant SAR processor for spaceborne imaging radar systems

Wai-Chi  Fang*, Charles Le, Stephanie Taft

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

10 Scopus citations

Abstract

A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.

Original languageEnglish
Article number1464614
Pages (from-to)420-423
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 1 Dec 2005
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: 23 May 200526 May 2005

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