On achieving low-power SoC clock tree synthesis by transition time planning via buffer library study

Huang Liang Chen*, Hung Ming Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Clock power dissipation has become a significant issue since it occupies around half of the total system power. Due to high working frequency in modern system designs, the transition time of the clock signal is extremely short. In order to keep up with this trend and to use less wire area, a large number of buffers have to be inserted in the network. As a consequence, short-circuit power of the clock buffers is no longer negligible. In this paper, we introduce a methodology which can be applied in global clock tree synthesis to achieve low short-circuit power. It is based on the analysis of any given buffer library in manipulating buffer transition time and hierarchical clustering of loads during buffer insertion. The experimental results are encouraging. Since there are very few works on gate/buffer sizing or buffer library analysis to overcome clocking power problem, we compare our approach with a greedy buffer sizing approach and obtain 13.7% clock power saving for a 10,000 flip-flop design under user-specified clock skew constraints.

Original languageEnglish
Title of host publication2006 IEEE International Systems-on-Chip Conference, SOC
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages203-206
Number of pages4
ISBN (Print)0780397819, 9780780397811
DOIs
StatePublished - 1 Jan 2006
Event2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
Duration: 24 Sep 200627 Sep 2006

Publication series

Name2006 IEEE International Systems-on-Chip Conference, SOC

Conference

Conference2006 IEEE International Systems-on-Chip Conference, SOC
CountryUnited States
CityAustin, TX
Period24/09/0627/09/06

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    Chen, H. L., & Chen, H. M. (2006). On achieving low-power SoC clock tree synthesis by transition time planning via buffer library study. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 203-206). [4063050] (2006 IEEE International Systems-on-Chip Conference, SOC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOCC.2006.283881