We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation ((TSANM) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower CTSNM- Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.