Novel Sub-10-nm Gate-all-around Si nanowire channel Poly-Si TFTs with raised source/drain

Yi Hsien Lu*, Po Yi Kuo, Yi Hong Wu, Yi Hsuan Chen, Tien-Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

19 Scopus citations

Abstract

We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7 time12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing sim 99 mV/dec, and high IOI OFF 107(VD) = V-1)without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

Original languageEnglish
Article number5671463
Pages (from-to)173-175
Number of pages3
JournalIEEE Electron Device Letters
Volume32
Issue number2
DOIs
StatePublished - 1 Feb 2011

Keywords

  • Gate-all-around (GAA)
  • nanowire (NW)
  • poly-Si thin-film transistors (poly-Si TFTs)
  • raised source/drain (S/D)

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