Over erasure, charge gain in low Vt state, and charge loss in high Vt state are found to be the most severe reliability issues in a localized trapping storage flash memory cell. In this paper, based on our understanding of physical mechanisms, we demonstrate that by adding vertical electrical field treatments during program/erase operation, the over erasure and data retentivities in high/low Vt states are significantly improved.
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - 1 Dec 2003|
|Event||IEEE International Electron Devices Meeting - Washington, DC, United States|
Duration: 8 Dec 2003 → 10 Dec 2003