Novel method for fabrication of tri-gated poly-Si nanowire field-effect transistors with sublithographic channel dimensions

Ko Hui Lee, Horng-Chih Lin, Tiao Yuan Huang

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

A high-performance short-channel tri-gated polycrystalline-silicon nanowire (NW) field-effect transistor is developed by using simple sidewall spacer and lateral etching techniques without employing costly lithographic tools. Channel length of 120 nm and NW thickness of 25 nm can be easily formed by the self-aligned process. The device exhibits superior electrical characteristics because of the strong gate controllability: a subthreshold swing of 102 mV/dec, drain induced barrier lowing of 74.4 mV/V, and extremely high I ON/IOFF ratio of 4.4 × 108(V d=1 V) are obtained.

Original languageEnglish
Article number6515595
Pages (from-to)720-722
Number of pages3
JournalIEEE Electron Device Letters
Volume34
Issue number6
DOIs
StatePublished - 3 Jun 2013

Keywords

  • Nanowire
  • polycrystalline-silicon (poly-Si)
  • self-aligned
  • short channel

Fingerprint Dive into the research topics of 'Novel method for fabrication of tri-gated poly-Si nanowire field-effect transistors with sublithographic channel dimensions'. Together they form a unique fingerprint.

  • Cite this