Novel junctionless silicon-oxide-nitride-oxide-silicon memory devices with field-enhanced poly-Si nanowire structure

Chia Hsin Chou, Wei Sheng Chan, Chun Yu Wu, I. Che Lee, Ta Chuan Liao, Chao Lung Wang, Kuang Yu Wang, Huang-Chung Cheng

Research output: Contribution to journalArticlepeer-review

Abstract

In this work, a novel gate-all-around (GAA) low-temperature poly-Si (LTPS) junctionless (JL) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory device with a field-enhanced nanowire (NW) structure has been proposed to improve the programing/erasing (P/E) performance. Each nanowire has three sharp corners fabricated by a sidewall spacer formation technique to obtain high local electrical fields. Owing to the higher carrier concentration in the channel and the high local electrical field from the three sharp corners, such a JL SONOS memory device exhibits a significantly enhanced P/E speed, a larger memory window, and better data retention properties than a conventional inversion mode NW-channel memory device.

Original languageEnglish
Article number084201
JournalJapanese Journal of Applied Physics
Volume54
Issue number8
DOIs
StatePublished - 1 Aug 2015

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