Novel isolation-scaling technology for NAND EEPROMs with the minimized program disturbance

Shinji Satoh*, Hiroyuki Hagiwara, Toru Tanzawa, Ken Takeuchi, Shirota Riichiro

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

29 Scopus citations

Abstract

This paper describes the key technology to realize a scaled NAND EEPROM with the minimized program disturbance. It has been clarified for the first time that the program disturbance caused by neighboring cells is drastically improved by reducing the field implantation dose. The limitation of conventional LOCOS width is estimated to be about 0.56 um. Moreover, a careful device design and an optimization of the bottom implantation are essential in a advanced STI cell.

Original languageEnglish
Pages (from-to)291-294
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
StatePublished - 1 Dec 1997
Event1997 International Electron Devices Meeting - Washington, DC, USA
Duration: 7 Dec 199710 Dec 1997

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