Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu, Howard Tang, Kuan Cheng Su, S. W. Sun

*Corresponding author for this work

Research output: Contribution to journalConference article

29 Scopus citations

Abstract

A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 angstroms) of the input stage in a 0.25-μm CMOS technology and sustain an ESD level above 2000 V without extra process modification.

Original languageEnglish
Pages (from-to)212-215
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 1 Jan 1998
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: 31 May 19983 Jun 1998

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