Novel high performance and reliability p-type floating gate N-channel flash EEPROM

Steve S. Chung*, C. M. Yih, S. T. Liaw, Z. H. Ho, S. S. Wu, C. J. Lin, D. S. Kuo, M. S. Liang

*Corresponding author for this work

Research output: Contribution to journalConference article

9 Scopus citations

Abstract

In the design of either n-channel or p-channel flash memory, conventional n-type poly-Si floating gate is normally used. None has been reported by using p-type as a floating gate in these cells. Recently, the p-type polysilicon gate technology in a dual gate CMOS process with p+ polysilicon gate has become matured. On the other hand, the multi-level memory cell technology for bit cost reduction has gained a lot of interests. One major requirement is that the threshold voltage distributions for various states must be separated to avoid read errors. However, widely spreaded distributions need higher programming voltages. In this paper, we proposed for the first time using p-type polysilicon as the floating gate in an n-channel flash memory in order to improve the cell performance and reliability. Results show that the flash cell with p-type floating gate has much better performance by comparing with conventional n-type floating-gate structure, such as faster programming/erasing speed, larger operation window, better read-disturb and endurance characteristics. Successful application of this flash memory cell for multi-level operation is also demonstrated.

Original languageEnglish
Pages (from-to)19-20
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
DOIs
StatePublished - 1 Dec 1999
EventProceedings of the 1999 Symposium on VLSI Technology - Kyoto, Jpn
Duration: 14 Jun 199916 Jun 1999

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