Novel FFT processor with parallel-in-parallel-out in normal order

Hsiang Sheng Hu*, Hsiao Yun Chen, Shyh-Jye Jou

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

A novel FFT processor that can provide parallel-in-parallel- out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm 2 by using 90 nm, 1V CMOS process.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages150-153
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 28 Apr 200930 Apr 2009

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period28/04/0930/04/09

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