Novel fabrication process of surface via-holes for GaAs power FETs

Hidetoshi Furukawa*, Takeshi Fukui, Tsuyoshi Tanaka, Atsushi Noma, Daisuke Ueda

*Corresponding author for this work

Research output: Contribution to conferencePaper

11 Scopus citations

Abstract

A simple new fabrication process of via-holes has been developed for GaAs power FETs. This process is featured by deep trench etching from the wafer surface followed by refilling the trench by conformal electro-plating. Surface Via-Hole (SVH) is engraved by extremely high rate ECR etching. We obtained the etching rate over 4 μm/min with completely anisotropic smooth profile. The conformal metal deposition around the trench is achieved by pulse-modulated electro-plating. The GaAs power FET with SVH showed better linearity than conventional wire-bonded one. The present SVH process is applicable to almost all the GaAs FETs or MMICs with very small area consumption and suitable for the high volume production.

Original languageEnglish
Pages251-254
Number of pages4
DOIs
StatePublished - 1 Dec 1998
EventProceedings of the 1998 20th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Atlanta, GA, USA
Duration: 1 Nov 19984 Nov 1998

Conference

ConferenceProceedings of the 1998 20th Annual IEEE Gallium Arsenide Integrated Circuit Symposium
CityAtlanta, GA, USA
Period1/11/984/11/98

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    Furukawa, H., Fukui, T., Tanaka, T., Noma, A., & Ueda, D. (1998). Novel fabrication process of surface via-holes for GaAs power FETs. 251-254. Paper presented at Proceedings of the 1998 20th Annual IEEE Gallium Arsenide Integrated Circuit Symposium, Atlanta, GA, USA, . https://doi.org/10.1109/GAAS.1998.722690