A simple new fabrication process of via-holes has been developed for GaAs power FETs. This process is featured by deep trench etching from the wafer surface followed by refilling the trench by conformal electro-plating. Surface Via-Hole (SVH) is engraved by extremely high rate ECR etching. We obtained the etching rate over 4 μm/min with completely anisotropic smooth profile. The conformal metal deposition around the trench is achieved by pulse-modulated electro-plating. The GaAs power FET with SVH showed better linearity than conventional wire-bonded one. The present SVH process is applicable to almost all the GaAs FETs or MMICs with very small area consumption and suitable for the high volume production.
|Number of pages||4|
|State||Published - 1 Dec 1998|
|Event||Proceedings of the 1998 20th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - Atlanta, GA, USA|
Duration: 1 Nov 1998 → 4 Nov 1998
|Conference||Proceedings of the 1998 20th Annual IEEE Gallium Arsenide Integrated Circuit Symposium|
|City||Atlanta, GA, USA|
|Period||1/11/98 → 4/11/98|