Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness

Ming-Dou Ker, Hsin Chyh Hsu, Jeng Jie Peng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 μm/0.5 μm has been successfully improved from the original 450 V to become 675 V in a 0.25 μm CMOS process.

Original languageEnglish
Title of host publicationProceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002
EditorsWai Kin Chim, John Thong, Wilson Tan, Kheng Chooi Lee
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages70-74
Number of pages5
ISBN (Electronic)0780374169
DOIs
StatePublished - 1 Jan 2002
Event9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002 - Singapore, Singapore
Duration: 12 Jul 2002 → …

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2002-January

Conference

Conference9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002
CountrySingapore
CitySingapore
Period12/07/02 → …

Keywords

  • CMOS integrated circuits
  • CMOS process
  • CMOS technology
  • Current measurement
  • Electrostatic discharge
  • Integrated circuit modeling
  • MOS devices
  • Robustness
  • Semiconductor device modeling
  • Stress

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