Novel design for testability of a mixed-signal VLSIC

E. McShane*, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi  Fang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolated between the circuit-under-test and idle circuits.

Original languageEnglish
Title of host publicationProceedings of the IEEE Great Lakes Symposium on VLSI
PublisherIEEE
Pages97-100
Number of pages4
ISBN (Print)0769501044
DOIs
StatePublished - 1 Dec 1999
EventProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Duration: 4 Mar 19996 Mar 1999

Publication series

NameProceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)1066-1395

Conference

ConferenceProceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
CityAnn Arbor, MI, USA
Period4/03/996/03/99

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