Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing

Tsun Ming Tseng, Bing Li, Ching Feng Yeh, Hsiang Chieh Jhan, Zuo-Min Tsai , Po-Hung Lin, Ulf Schlichtmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in recent years. Since the performance of CMOS RFICs is very sensitive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to generate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both performance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout generation time is significantly reduced from weeks to half an hour.

Original languageEnglish
Title of host publicationProceedings of the 53rd Annual Design Automation Conference, DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450342360
DOIs
StatePublished - 5 Jun 2016
Event53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States
Duration: 5 Jun 20169 Jun 2016

Publication series

NameProceedings - Design Automation Conference
Volume05-09-June-2016
ISSN (Print)0738-100X

Conference

Conference53rd Annual ACM IEEE Design Automation Conference, DAC 2016
CountryUnited States
CityAustin
Period5/06/169/06/16

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