A novel circuit technique was presented to improve the read performance of static random access memory (SRAM) storage. The technique was used to suppress parasitic bipolar currents in partially depleted (PD) silicon on insulator (SOI) technology. The concepts were demonstrated by employing 1.5 V, 0.18 μm SOI technology. Simulation results indicated an increase in read current and performance by 18% at higher temperatures and by 24% at lower temperatures.
|Number of pages||2|
|State||Published - 1 Jan 2001|
|Event||2001 IEEE International SOI Conference - Durango, CO, United States|
Duration: 1 Oct 2001 → 4 Oct 2001
|Conference||2001 IEEE International SOI Conference|
|Period||1/10/01 → 4/10/01|