Novel circuits to improve SRAM performance in PD/SOI technology

R. V. Joshi*, A. Bhavnagarwala, L. L. Hsu, C. T. Chuang, Wei Hwang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations


A novel circuit technique was presented to improve the read performance of static random access memory (SRAM) storage. The technique was used to suppress parasitic bipolar currents in partially depleted (PD) silicon on insulator (SOI) technology. The concepts were demonstrated by employing 1.5 V, 0.18 μm SOI technology. Simulation results indicated an increase in read current and performance by 18% at higher temperatures and by 24% at lower temperatures.

Original languageEnglish
Number of pages2
StatePublished - 1 Jan 2001
Event2001 IEEE International SOI Conference - Durango, CO, United States
Duration: 1 Oct 20014 Oct 2001


Conference2001 IEEE International SOI Conference
CountryUnited States
CityDurango, CO

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